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preliminary: the specification of this device are subject to change without notice. please contact your nearest hitachi? sales dept. regarding specification. hm62a16256cbpi series wide temperature range version 4 m sram (256-kword 16-bit) ade-203-1102 (z) preliminary rev. 0.0 sep. 8, 1999 description the hitachi hm62a16256cbpi series is 4-mbit static ram organized 262,144-word 16-bit. hm62a16256cbpi series has realized higher density, higher performance and low power consumption by employing hi-cmos process technology. it offers low power standby power dissipation; therefore, it is suitable for battery backup systems. it is packaged in 48 bumps chip size package with 0.75 mm bump pitch for high density surface mounting. hm62a16256cbpi is suitable for the application of the mobile phone to reduce both the mount space and weight. features ? single 1.8 v supply: 1.65 v to 2.0 v ? fast access time: 70 ns (max) ? power dissipation: ? active: tbd (typ) ? standby: 0.9 m w (typ) ? completely static memory. ? no clock or timing strobe required ? equal access and cycle times ? common data input and output. ? three state output ? battery backup operation. ? 2 chip selection for battery backup ? temperature range: ?0 to +85 c
hm62a16256cbpi series 2 ordering information type no. access time package hm62a16256clbpi-7 70 ns 48-bumps csp with 0.75 mm bump pitch (tbd) HM62A16256CLBPI-7SL 70 ns
hm62a16256cbpi series 3 pin arrangement (top view) 48-bumps csp a b c d e f g h 1 2 3 4 5 6 lb i/o8 i/o9 v ss v cc i/o14 i/o15 nc oe ub i/o10 i/o11 i/o12 i/o13 nc a8 a3 a5 a17 nc a14 a0 a12 a9 a1 a4 a6 a7 a16 a15 a13 a10 a2 cs1 i/o1 i/o3 i/o4 i/o5 we a11 cs2 i/o0 i/o2 v cc v ss i/o6 i/o7 nc pin description pin name function a0 to a17 address input i/o0 to i/o15 data input/output cs1 chip select 1 cs2 chip select 2 we write enable oe output enable lb lower byte select ub upper byte select v cc power supply v ss ground nc no connection
hm62a16256cbpi series 4 block diagram tbd
hm62a16256cbpi series 5 operation table cs1 cs2 we oe ub lb i/o0 to i/o7 i/o8 to i/o15 operation h high-z high-z standby l high-z high-z standby h h high-z high-z standby l h h l l l dout dout read l h h l h l dout high-z lower byte read l h h l l h high-z dout upper byte read lhl l l din din write lhl h l din high-z lower byte write lhl l h high-z din upper byte write lhhh high-z high-z output disable note: h: v ih , l: v il , : v ih or v il absolute maximum ratings parameter symbol value unit power supply voltage relative to v ss v cc ?.3 to + 2.5 v terminal voltage on any pin relative to v ss v t ?.3* 1 to v cc + 0.3* 2 v power dissipation p t 1.0 w storage temperature range tstg ?5 to +125 c storage temperature range under bias tbias ?0 to +85 c notes: 1. v t min: ?.0 v for pulse half-width 20 ns. 2. maximum voltage is +2.5 v. dc operating conditions parameter symbol min typ max unit note supply voltage v cc 1.65 1.8 2.0 v v ss 000v input high voltage v ih 1.4 v cc + 0.2 v input low voltage v il ?.2 0.4 v 1 ambient temperature range ta ?0 85 c note: 1. v il min: ?.0 v for pulse half-width 20 ns.
hm62a16256cbpi series 6 dc characteristics parameter symbol min typ * 1 max unit test conditions input leakage current |i li | 1 m a vin = v ss to v cc output leakage current |i lo | 1 m a cs1 = v ih or cs2 = v il or oe = v ih or we = v il , or l b = ub =v ih v i/o = v ss to v cc operating current i cc 2 ma cs1 = v il , cs2 = v ih , others = v ih /v il , i i/o = 0 ma average operating current i cc1 25 ma min. cycle, duty = 100%, i i/o = 0 ma, cs1 = v il , cs2 = v ih , others = v ih /v il i cc2 3 ma cycle time = 1 m s, duty = 100%, i i/o = 0 ma, cs1 0.2 v, cs2 3 v cc ?0.2 v v ih 3 v cc ?0.2 v, v il 0.2 v standby current i sb 0.3 ma cs2 = v il standby current i sb1 * 2 0.5 5 m a 0 v vin (1) 0 v cs2 0.2 v or (2) cs1 3 v cc ?0.2 v, cs2 3 v cc ?0.2 v i sb1 * 3 0.5 2 m a output high voltage v oh v cc ?0.2 v i oh = ?00 m a output low voltage v ol 0.2 v i ol = 100 m a notes: 1. typical values are at v cc = 1.8 v, ta = +25 c and not guaranteed. 2. this characteristic is guaranteed only for l-version. 3. this characteristic is guaranteed only for l-sl version. capacitance (ta = +25 c, f = 1.0 mhz) parameter symbol min typ max unit test conditions note input capacitance cin 8 pf vin = 0 v 1 input/output capacitance c i/o 10 pf v i/o = 0 v 1 note: 1. this parameter is sampled and not 100% tested.
hm62a16256cbpi series 7 ac characteristics (ta = ?0 to +85 c, v cc = 1.65 v to 2.0 v, unless otherwise noted.) test conditions ? input pulse levels: v il = 0.2 v, v ih = v cc ?0.2 v ? input rise and fall time: 5 ns ? input and output timing reference levels: 0.9 v ? output load: see figure (including scope and jig) dout 30pf r1 v tm v tm = 1.8 v r2 r1 = 3070 w r2 = 3150 w
hm62a16256cbpi series 8 read cycle hm62a16256cbpi -7 parameter symbol min max unit notes read cycle time t rc 70 ns address access time t aa ?0ns chip select access time t acs1 ?0ns t acs2 ?0ns output enable to output valid t oe ?0ns output hold from address change t oh 10 ns lb , ub access time t ba ?0ns chip select to output in low-z t clz1 10 ns 2, 3 t clz2 10 ns 2, 3 lb , ub enable to low-z t blz 5 ns 2, 3 output enable to output in low-z t olz 5 ns 2, 3 chip deselect to output in high-z t chz1 0 25 ns 1, 2, 3 t chz2 0 25 ns 1, 2, 3 lb , ub disable to high-z t bhz 0 25 ns 1, 2, 3 output disable to output in high-z t ohz 0 25 ns 1, 2, 3
hm62a16256cbpi series 9 write cycle hm62a16256cbpi -7 parameter symbol min max unit notes write cycle time t wc 70 ns address valid to end of write t aw 60 ns chip selection to end of write t cw 60 ns 5 write pulse width t wp 50 ns 4 lb , ub valid to end of write t bw 55 ns address setup time t as 0 ns 6 write recovery time t wr 0 ns 7 data to write time overlap t dw 30 ns data hold from write time t dh 0ns output active from end of write t ow 5 ns 2 output disable to output in high-z t ohz 0 25 ns 1, 2 write to output in high-z t whz 0 25 ns 1, 2 notes: 1. t chz , t ohz , t whz and t bhz are defined as the time at which the outputs achieve the open circuit conditions and are not referred to output voltage levels. 2. this parameter is sampled and not 100% tested. 3. at any given temperature and voltage condition, t hz max is less than t lz min both for a given device and from device to device. 4. a write occures during the overlap of a low cs1 , a high cs2, a low we and a low lb or a low ub . a write begins at the latest transition among cs1 going low, cs2 going high, we going low and lb going low or ub going low. a write ends at the earliest transition among cs1 going high, cs2 going low, we going high and lb going high or ub going high. t wp is measured from the beginning of write to the end of write. 5. t cw is measured from the later of cs1 going low or cs2 going high to the end of write. 6. t as is measured from the address valid to the beginning of write. 7. t wr is measured from the earliest of cs1 or we going high or cs2 going low to the end of write cycle.
hm62a16256cbpi series 10 timing waveform read cycle t aa t acs1 t acs2 t clz2 t clz1 t blz t ba t oh t rc valid data address dout valid address high impedance cs1 cs2 lb , ub oe * 1, 2, 3 * 1, 2, 3 * 2, 3 * 2, 3 * 2, 3 * 1, 2, 3 t olz * 2, 3 * 1, 2, 3 t oe t chz1 t chz2 t bhz t ohz
hm62a16256cbpi series 11 write cycle (1) ( we clock) address we t wc t aw t wp * 4 t wr * 7 t cw * 5 t cw * 5 t bw t as * 6 t ow * 2 t whz * 1, 2 t dw t dh valid address valid data cs1 lb , ub dout din high impedance cs2
hm62a16256cbpi series 12 write cycle (2) ( cs clock, oe = v ih ) address we t wc t aw t wp * 4 t wr * 7 t cw * 5 t cw * 5 t bw t as * 6 t dw t dh valid address valid data lb , ub dout din high impedance cs2 cs1
hm62a16256cbpi series 13 write cycle (3) ( lb , ub clock, oe = v ih ) address we t wc t aw t wp * 4 t cw * 5 t cw * 5 t bw t wr * 7 t dw t dh valid address valid data lb , ub dout din high impedance cs2 cs1 t as * 6
hm62a16256cbpi series 14 low v cc data retention characteristics (ta = ?0 to +85 c) parameter symbol min typ * 4 max unit test conditions * 3 v cc for data retention v dr 1.0 2.0 v vin 3 0v (1) 0 v cs2 0.2 v or (2) cs2 3 v cc ?0.2 v cs1 3 v cc ?0.2 v or (3) lb = ub 3 v cc ?0.2 v cs2 3 v cc ?0.2 v cs1 0.2 v data retention current i ccdr * 1 0.3 3 m av cc = 1.2 v, vin 3 0v (1) 0 v cs2 0.2 v or (2) cs2 3 v cc ?0.2 v, cs1 3 v cc ?0.2 v or (3) lb = ub 3 v cc ?0.2 v cs2 3 v cc ?0.2 v cs1 0.2 v i ccdr * 2 0.3 2 m a chip deselect to data retention time t cdr 0 ns see retention waveform operation recovery time t r t rc * 5 ns notes: 1. this characteristic is guaranteed only for l-version. 2. this characteristic is guaranteed only for l-sl version. 3. cs2 controls address buffer, we buffer, cs1 buffer, oe buffer, lb , ub buffer and din buffer. if cs2 controls data retention mode, vin levels (address, we , oe , cs1 , lb , ub , i/o) can be in the high impedance state. if cs1 controls data retention mode, cs2 must be cs2 3 v cc ?0.2 v or 0 v cs2 0.2 v. the other input levels (address, we , oe , lb , ub , i/o) can be in the high impedance state. 4. typical values are at v cc = 1.2 v, ta = +25?c and not guaranteed. 5. t rc = read cycle time.
hm62a16256cbpi series 15 low v cc data retention timing waveform (1) ( cs1 controlled) cc v 1.65 v 1.4 v 0 v cs1 t cdr t r cs1 v ?0.2 v cc 3 dr v data retention mode low v cc data retention timing waveform (2) (cs2 controlled) cc v 1.65 v 0.4 v 0 v cs2 cdr t r 0 v cs2 0.2 v dr v data retention mode t < < low v cc data retention timing waveform (3) ( lb , ub controlled) cc v 1.65 v 1.4 v 0 v lb , ub t cdr t r lb , ub v ?0.2 v cc 3 dr v data retention mode
hm62a16256cbpi series 16 package dimensions hm62a16256clbpi series (tbd) hitachi code jedec eiaj weight (reference value) tbd ? ? tbd unit: mm 6.5 0.25 0.05 0.076 c f 0.20 ab 6.5 c a 48 f 0.35 0.05 details of the part a m c f 0.10 m 0.27 0.03 (0.6) 1.2 max a b c 654321 a b c d e f g h 0.75 1.375 (3.75) 0.75 (5.25) 0.625 pin 1 index
hm62a16256cbpi series 17 cautions 1. hitachi neither warrants nor grants licenses of any rights of hitachi? or any third party? patent, copyright, trademark, or other intellectual property rights for information contained in this document. hitachi bears no responsibility for problems that may arise with third party? rights, including intellectual property rights, in connection with use of the information contained in this document. 2. products and product specifications may be subject to change without notice. confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. hitachi makes every attempt to ensure that its products are of high quality and reliability. however, contact hitachi? sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. design your application so that the product is used within the ranges guaranteed by hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the hitachi product. 5. this product is not designed to be radiation resistant. 6. no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from hitachi. 7. contact hitachi? sales office for any questions regarding this document or hitachi semiconductor products. hitachi, ltd. semiconductor & integrated circuits. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan tel: tokyo (03) 3270-2111 fax: (03) 3270-5109 copyright ?hitachi, ltd., 1998. all rights reserved. printed in japan. hitachi asia pte. ltd. 16 collyer quay #20-00 hitachi tower singapore 049318 tel: 535-2100 fax: 535-1533 url northamerica : http:semiconductor.hitachi.com/ europe : http://www.hitachi-eu.com/hel/ecg asia (singapore) : http://www.has.hitachi.com.sg/grp3/sicd/index.htm asia (taiwan) : http://www.hitachi.com.tw/e/product/sicd_frame.htm asia (hongkong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm japan : http://www.hitachi.co.jp/sicd/indx.htm hitachi asia ltd. taipei branch office 3f, hung kuo building. no.167, tun-hwa north road, taipei (105) tel: <886> (2) 2718-3666 fax: <886> (2) 2718-8180 hitachi asia (hong kong) ltd. group iii (electronic components) 7/f., north tower, world finance centre, harbour city, canton road, tsim sha tsui, kowloon, hong kong tel: <852> (2) 735 9218 fax: <852> (2) 730 0281 telex: 40815 hitec hx hitachi europe ltd. electronic components group. whitebrook park lower cookham road maidenhead berkshire sl6 8ya, united kingdom tel: <44> (1628) 585000 fax: <44> (1628) 778322 hitachi europe gmbh electronic components group dornacher stra? 3 d-85622 feldkirchen, munich germany tel: <49> (89) 9 9180-0 fax: <49> (89) 9 29 30 00 hitachi semiconductor (america) inc. 179 east tasman drive, san jose,ca 95134 tel: <1> (408) 433-1990 fax: <1>(408) 433-0223 for further information write to:
hm62a16256cbpi series 18 revision record rev. date contents of modification drawn by approved by 0.0 sep. 8, 1999 initial issue

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